2d self-aligned via first process flow

ABSTRACT

A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

RELATED APPLICATION

The present application is a Divisional of application Ser. No.14/707,443, filed on May 8, 2015, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the manufacture of semiconductordevices with vias or interconnects. The present disclosure isparticularly applicable to the 10 nanometer (nm) technology node andbeyond.

BACKGROUND

To provide electrical conductivity between layers in a semiconductordevice, a via or interconnect may be formed through an interlayerdielectric (ILD). The via is generally formed using a photolithographicmask. The via is then lined with a barrier and filled with anelectrically conductive material such as copper (Cu) to provideelectrical conductivity between two or more metal layers, e.g., Mx andMx+1. Each of the metal layers is also generally formed using arespective photolithographic mask.

A known approach for forming two-dimensional (2D) self-aligned viasinvolves forming the Mx+1 layer before forming the vias and thenpatterning the vias at the bottom of trenches created by removing theMx+1 dummy lines to form the Mx+1 layer. In this approach, a nitride capremains over the entire Mx layer, which increases the capacitance of thesemiconductor device and, therefore, reduces performance. Further, aseparate photolithography mask is required for forming each metal layerand the vias, which increases processing costs.

A need therefore exists for methodology enabling a less expensive 2Dself-aligned via formation process and a reduction of devicecapacitance, and the resulting device.

SUMMARY

An aspect of the present disclosure is a method of lithographicallyforming 2D self-aligned vias before forming a subsequent metal layerwhile reducing overall capacitance of the resulting device.

Another aspect of the present disclosure is a mechanically robust deviceincluding 2D self-aligned vias and minimal Mx line nitride.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method including: forming parallel dummy firstmetal lines in a first silicon oxycarbide (SiOC) layer and extending ina first direction; replacing the dummy first metal lines with firstmetal lines, each first metal line having a nitride cap; forming a firstsoftmask stack over the nitride cap and the first SiOC layer; patterninga plurality of vias through the softmask stack down to the first metallines, the plurality of vias self-aligned along a second direction;removing the first softmask stack; forming parallel dummy second metallines over the first metal lines and extending in the second direction;forming a second SiOC layer between the dummy second metal lines on thefirst SiOC layer; and replacing the dummy second metal lines with secondmetal lines, the second metal lines electrically connected to the firstmetal lines through at least one of the vias.

Aspects of the present disclosure include forming the dummy first linesby: forming an oxide layer over a silicon substrate; forming the firstSiOC layer over the oxide layer; forming parallel trenches in the firstSiOC layer extending in the first direction; filling the trenchespartially with amorphous silicon (a-Si); forming a nitride layer overthe a-Si and the first SiOC layer; and planarizing the nitride layerdown to the first SiOC layer. Other aspects include replacing the dummyfirst metal lines with the first metal lines by: removing the a-Si andnitride layer from the trenches down to the oxide layer; forming abarrier layer over the trenches and first SiOC layer; forming a firstmetal layer over the barrier layer; planarizing the first metal layer;recessing the first metal layer; forming the nitride cap over therecessed first metal layer and the first SiOC layer; and planarizing thenitride cap down to the first SiOC layer. Further aspects includeforming the softmask stack by: forming a spin-on-hardmask (SOH) layerover the nitride cap and first SiOC layer; forming a silicon oxynitrdie(SiON) layer over the SOH layer; forming a buried anti-reflectivecoating (BARC) layer over the SiON layer; and forming a photoresistlayer over the BARC layer. Additional aspects include patterning theplurality of vias by: forming a plurality of holes by lithography in thephotoresist down to the BARC; transferring the plurality of holes downto the nitride cap; and etching the plurality of holes selective to thefirst metal lines and the first SiOC layer.

Another aspect includes forming the dummy second metal lines by: forminga dummy a-Si layer over the nitride cap and first SiOC layer and in theplurality of vias; forming a second softmask stack over the dummy a-Silayer; and patterning the second softmask stack and dummy a-Si layerdown to the nitride cap and first SiOC layer. Other aspects includeforming the second softmask stack by: forming a nitride layer over thedummy a-Si layer, the nitride layer having a thickness greater than athickness of the nitride cap; forming a second dummy a-Si layer over thenitride layer; forming a SOH layer over the other a-Si layer; forming aSiON layer over the SOH layer; forming a BARC layer over the SiON layer;and forming a photoresist layer over the BARC layer. Further aspectsinclude patterning the second softmask stack and dummy a-Si layer by:patterning the photoresist layer into parallel lines, the parallel linespatterned along the second direction; and etching between the parallellines down to the nitride cap and the first SiOC layer. Additionalaspects include removing the a-Si layer from the plurality of vias andthe nitride cap between the parallel lines down to the first metallines; and removing the second dummy a-Si layer and the SOH, SiON, BARC,and photoresist layers. Another aspect includes removing the nitride capbetween the parallel lines concurrently with removing the a-Si layerfrom the plural vias. Other aspects include replacing the dummy secondmetal lines with second metal lines by: forming the second SiOC layerover and between the dummy second metal lines; planarizing the secondSiOC layer down to the nitride layer; etching the dummy second metallines down to the nitride cap and the first SiOC layer, forming paralleltrenches; forming a barrier layer over the second SiOC layer and thetrenches and in the plurality of vias; forming a second metal layer overthe barrier layer; and planarizing the second metal layer down thesecond SiOC layer.

Another aspect of the present disclosure is a device including: asilicon substrate; an oxide layer formed over the substrate; a firstSiOC layer formed over the oxide layer; parallel first metal linesrecessed in the first SiOC layer and extending in a first direction; anarray of nitride caps and vias over the first metal lines, formed in therecessed first SiOC; parallel second metal lines extending in a seconddirection perpendicular to the first direction, the second metal linesbeing formed over the nitride caps, the vias, and the first SiOC layer;and a second SiOC between the second metal lines, down to the first SiOCand the first metal lines.

Aspects of the device include the nitride caps being formed to athickness of 15 nm to 40 nm. Other aspects include the plurality of viasbeing resized by the formation of the second metal lines. Furtheraspects include the plurality of vias being self-aligned in both thefirst and the second directions.

A further aspect of the present disclosure is a method including:forming parallel first metal lines in a first SiOC layer and extendingin a first direction, the first metal lines having a nitride cap;forming a first softmask stack over the nitride cap and first SiOClayer; forming a plurality of vias through the first softmask stack downto the first metal lines, the plurality of vias self-aligned along asecond direction; removing the first softmask; and forming second metallines in a second SiOC layer and extending in the second direction, thesecond metal lines electrically connected to the first metal linesthrough at least one of the plurality of vias.

Aspects of the present disclosure include forming the first metal linesby: forming an oxide layer over a silicon substrate; forming the firstSiOC layer over the oxide layer; forming parallel trenches in the firstSiOC layer in the first direction; filling the trenches partially witha-Si; forming a nitride layer over the a-Si and the first SiOC layer;planarizing the nitride layer down to the first SiOC layer; removing thea-Si and nitride layer from the trenches down to the oxide layer;forming a barrier layer over the trenches and first SiOC layer; forminga first metal layer over the barrier layer; planarizing the first metallayer; recessing the first metal layer; forming the nitride cap over therecessed first metal layer and the first SiOC layer; and planarizing thenitride cap down to the first SiOC layer. Other aspects include formingthe first softmask and the plurality of vias by: forming a SOH layerover the nitride cap and first SiOC layer; forming a SiON layer over theSOH layer; forming a BARC layer over the SiON layer; forming aphotoresist layer over the BARC layer; forming a plurality of holes bylithography in the photoresist layer down to the BARC; transferring theplurality of holes down to the nitride cap; and etching the plurality ofholes selective to the first metal lines and first SiOC layer. Furtheraspects include forming dummy metal lines prior to forming the secondmetal lines by: forming a first a-Si layer over the nitride cap andfirst SiOC layer and in the plurality of vias; forming a nitride layerover the first a-Si layer, the nitride layer having a thickness greaterthan a thickness of the nitride cap; forming a second a-Si layer overthe nitride layer; forming a SOH layer over the second a-Si layer;forming a SiON layer over the SOH layer; forming a BARC layer over theSiON layer; forming a photoresist layer over the BARC layer; patterningthe photoresist layer into parallel lines, the parallel lines patternedalong the second direction; etching between the parallel lines down tothe nitride cap and the first SiOC layer; removing the a-Si layer fromthe plurality of vias from opposite sides of each parallel line;removing the second a-Si layer and the SOH, SiON, BARC, and photoresistlayers; and removing the nitride cap from opposite sides of each dummymetal line. Additional aspects include forming the second metal linesby: forming the second SiOC layer over the dummy lines; planarizing thesecond SiOC layer down to the nitride layer; etching the dummy linesdown to the nitride cap and the first SiOC layer, forming paralleltrenches; forming a barrier layer over the second SiOC layer and thetrenches and in the plurality of vias; forming a second metal layer overthe barrier layer; and planarizing the second metal layer down thesecond SiOC layer.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIGS. 1 through 14B schematically illustrate a process flow for forming2D self-aligned vias before forming a subsequent metal layer, inaccordance with an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments. Inaddition, unless otherwise indicated, all numbers expressing quantities,ratios, and numerical properties of ingredients, reaction conditions,and so forth used in the specification and claims are to be understoodas being modified in all instances by the term “about.”

The present disclosure addresses and solves the current problems of aneed for separate photolithographic masks for forming metal layers andvias, difficult via patterning due to aspect ratio, and high capacitanceof nitride attendant upon forming vias through metal line trenches in asemiconductor device.

Methodology in accordance with embodiments of the present disclosureincludes forming parallel dummy first metal lines in a first SiOC layerand extending in a first direction. The dummy first metal lines arereplaced with first metal lines, each first metal line having a nitridecap. A first softmask stack is formed over the nitride cap and the firstSiOC layer, and a plurality of vias are patterned through the softmaskstack down to the first metal lines, the plurality of vias self-alignedalong a second direction. The first softmask stack is removed andparallel dummy second metal lines are formed over the first metal linesand extended in the second direction. A second SiOC layer is formedbetween the dummy second metal lines on the first SiOC layer, and thedummy second metal lines are replaced with second metal lines. Thesecond metal lines are electrically connected to the first metal linesthrough at least one of the vias.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

Adverting to FIG. 1 (FIG. 1 is an orthographic view of a Mx stack), anoxide layer 101 is formed on a silicon substrate 103. Dummy metal lines105 are formed, e.g., of a-Si, on top of the oxide layer 101 along witha nitride cap layer 107. Next, a SiOC layer 109 is formed over the dummymetal lines 105 and the nitride cap layer 107 and then planarized, e.g.,by CMP, down to the nitride cap layer 107. The dummy lines 105 may beformed, for example, by self-aligned double patterning (SADP) orself-aligned quadruple patterning (SAQP) to achieve a small pitch, e.g.,a pitch less than 64 nm, such as 10 nm to 35 nm. The dummy metal lines105 may be formed, for example, with a width of 10 nm to 35 nm and aheight of 30 nm to 120 nm (including the nitride cap layer 107).

Next, the dummy metal lines 105 are removed down to the oxide layer 101,e.g., by wet bromide reactive ion etching (RIE) or aqueoustetramethylammonium hydroxide (TMAH) wet etching, forming paralleltrenches 201, as depicted in FIG. 2 (FIGS. 2 and 3 depict across-sectional view of the Mx stack along the x direction). A barrierlayer (not shown for illustrative convenience) is then formed, e.g., oftantalum nitride (TaN), titanium nitride (TiN), or ruthenium (Ru), overthe parallel trenches 201 and the SiOC layer 109. Thereafter, metallines 301 are formed, for example, of tungsten (W), cobalt (Co), or Cu,e.g., Co, over the barrier layer and then planarized, e.g., by CMP, downto the SiOC layer 109, as depicted in FIG. 3. Adverting to FIG. 4 (FIGS.4 and 5 depict a cross-sectional view of the Mx stack along the xdirection), the metal lines 301 are recessed, e.g., 15 nm to 40 nm.Next, a nitride cap layer 501 is deposited over the recessed metal lines301 and the SiOC layer 109 and then planarized, e.g., by CMP, down tothe SiOC layer 109, as depicted in FIG. 5.

Adverting to FIG. 6 (FIG. 6 is an orthographic view of a softmask stackformed on top of the Mx stack), a softmask stack 601 is formed over thenitride cap layer 501 and the SiOC layer 109. The softmask stack 601 maybe formed, for example, of a SOH layer 603, a SiON layer 605, a BARClayer 607, and a photoresist layer 609. Next, holes 611 are formed bylithography in the photoresist layer 609 down to the BARC layer 607. Theholes 611 are then transferred down from the BARC layer 607 to thenitride cap layer 501 and the softmask stack 601 is removed. Thereafter,the holes 611 are etched, e.g., by nitride RIE, selective to the metallines 301 and the SiOC 109 forming vias 701, as depicted in FIG. 7. Theresulting vias 701 are one-dimensional (1D) self-aligned along the xdirection because although the holes 611 are larger in the x directionthan the vias 701, the resulting vias 701 are resized by the selectiveetching, which resolves issues with overlay.

Once the vias 701 are formed, dummy metal lines may be formed for asubsequent metal layer, e.g., Mx+1. Adverting to FIGS. 8A and 8B (FIG.8A depicts a cross-sectional view of the Mx stack and the start of theMx+1 stack along the x direction and FIG. 8B depicts a cut of FIG. 8Aalong the y direction), a dummy a-Si layer 801 is formed over thenitride cap 501 and the SiOC layer 109 and in the vias 701 (as shown bythe dashed circle 803). Next, a softmask stack 901 is formed over thedummy a-Si layer 801, as depicted in FIG. 9 (FIG. 9 is an orthographicview of a softmask stack formed on top of the Mx stack). The softmaskstack 901 may be formed, for example, of a nitride cap layer 903, a-Silayer 905, a SOH layer 907, a SiON layer 909, a BARC layer 911, and aphotoresist layer 913. Thereafter, the photoresist layer 913 ispatterned into parallel lines 913′ in the y direction. While the x and ydirections are depicted at a right angle, the x and y directions onlyneed to be different from each other to enable 2D patterning.

FIG. 10A depicts an orthographic view of the Mx stack and Mx+1 dummylines and FIG. 10B is an overhead view of FIG. 10A. Adverting to FIGS.10A and 10B, the softmask stack 901 is patterned, and the dummy a-Silayer 801 is etched by an anisotropic a-Si etch between the parallellines 913′ down to the nitride cap 501 and the SiOC layer 109. Dummymetal lines 801′, which include the nitride cap layer 903, are formed.The anisotropic a-Si etch is performed with enough overetch to removethe dummy a-Si 801 in the vias 701. Consequently, the metal lines 301are visible through the vias 701, as depicted in FIG. 10B. In addition,as a result of the formation of the dummy metal lines 801′, the vias 701are now also 1D self-aligned along the y direction.

The nitride cap 501 is also removed between the parallel lines 913′ by anitride anisotropic etch, as depicted in FIGS. 11A and 11B (FIG. 11A isan orthographic view of the Mx stack and Mx+1 dummy lines correspondingto the dashed line 1101, and FIG. 11B is an overhead view of FIG. 11A).The nitride cap layer 903 needs to be formed with a thickness greaterthan the thickness of the nitride cap layer 501 so that at least someportion of the nitride cap layer 903 will remain after the nitrideanisotropic etching. After the nitride anisotropic etch, the nitride cap501 only remains under the dummy lines 801′. The intent is to strip asmuch of the nitride cap 501 as possible because nitride has a highcapacitance value. The areas where the nitride cap 501 was removed willsubsequently be filled with a SiOC layer, reducing the overallcapacitance of the resulting device. In an alternative embodiment, thenitride cap 501 may be removed between the parallel lines 913′ at thesame time as the anisotropic a-Si etch of FIGS. 10A and 10B.

Adverting to FIG. 12 (FIG. 12 is an orthographic view of the Mx layerand the Mx+1 dummy lines), a SiOC layer 1201 is formed over and betweenthe dummy metal lines 801′ and then planarized, e.g., by CMP, down tothe nitride cap layer 903. The dummy metal lines 801′ and the nitridecap layer 903 are then removed down to the nitride layer 501 and theSiOC layer 109, e.g., by etching, forming parallel trenches 1301 asdepicted in FIG. 13 (FIG. 13 is an overhead orthographic view of theMx+1 stack). With the dummy metal lines 801′ removed, the metal lines301 can be seen through the vias 701 as well as the remaining nitridecap layer 501, which was previously masked by the dummy metal lines801′.

FIGS. 14A and 14B are orthographic views of the resulting device withthe SiOC layers 109 and 1201 of FIG. 14A shown transparent. Adverting toFIGS. 14A and 14B, a barrier layer 1401 is formed over the SiOC layer1201 and the trenches 1301 and in the vias 701 so that it can connectwith the barrier layer of the metal lines 301, as shown by dashed circle1403. Next, metal lines 1405 are formed, e.g., of Cu, over the barrierlayer 1401 and then planarized, e.g., by CMP, down to the SiOC layer1201. Both metal lines may be formed of the same conductive material,e.g., Cu, or they may be formed of different materials, e.g., Co for Mxand Cu for Mx+1. Consequently, a via 701 is formed at each intersectionof the metal lines 301 and 1405, forming a regular array. Most of thevias 701 are filled with the nitride cap layer 501, but some as shown bythe dashed circle 1403 electrically connect the metal lines 301 and themetal lines 1405 through the respective barrier layers. The result is arobust mechanical structure that will not collapse with subsequentbumping processes.

The embodiments of the present disclosure can achieve several technicaleffects including forming vias lithographically before forming asubsequent metal layer so that the Via and Mx cut masks may be combinedwhile keeping it a 2D self-aligned process. In addition, 50% of the Mxline nitride cap is replaced with SiOC reducing the capacitance of theresulting device. This effect can potentially be achieved at no extracost where the nitride removal is integrated with the Mx+1 dummy a-Sietch and the SiOC deposition is part of the standard dielectricdeposition between Mx+1 dummy lines. Further, via patterning is nolonger required at the bottom of the Mx+1 trench, which is potentiallydifficult because of aspect ratio. Embodiments of the present disclosureenjoy utility in various industrial applications as, for example,microprocessors, smart phones, mobile phones, cellular handsets, set-topboxes, DVD recorders and players, automotive navigation, printers andperipherals, networking and telecom equipment, gaming systems, anddigital cameras. The present disclosure therefore enjoys industrialapplicability in any of various types of highly integrated semiconductordevices in the 10 nm technology node and beyond.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A device comprising: a silicon substrate; anoxide layer formed over the substrate; a first silicon oxycarbide (SiOC)layer formed over the oxide layer; parallel first metal lines recessedin the first SiOC layer and extending in a first direction; an array ofnitride caps and vias over the first metal lines, formed in the recessedfirst SiOC; parallel second metal lines extending in a second directionperpendicular to the first direction, the second metal lines beingformed over the nitride caps, the vias, and the first SiOC layer; and asecond SiOC between the second metal lines, down to the first SiOC andthe first metal lines.
 2. The device according to claim 1, wherein thenitride caps are formed to a thickness of 15 nanometer (nm) to 40 nm. 3.The device according to claim 1, wherein the plurality of vias areresized by the formation of the second metal lines.
 4. The deviceaccording to claim 3, wherein the plurality of vias are self-aligned inboth the first and the second directions.
 5. The device according toclaim 1, wherein the first and second metal lines comprise tungsten (W),cobalt (Co), or copper (Cu).
 6. The device according to claim 1, whereinthe first metal lines have a width of 10 nm to 35 nm and a height of 30nm to 120 nm, inclusive of the nitride cap.
 7. A device comprising:parallel first metal lines formed in a first silicon oxycarbide (SiOC)layer and extending in a first direction, each first metal line having anitride cap; a plurality of vias extending down to the first metallines, the plurality vias extending along a second direction; parallelsecond metal lines formed in a second SiOC layer over the first metallines and extending in the second direction perpendicular to the firstdirection, the second metal lines electrically connected to the firstmetal lines through at least one of the vias.
 8. The device according toclaim 7, wherein each second metal line has a nitride cap.
 9. The deviceaccording to claim 7, nitride caps are formed to a thickness of 15nanometer (nm) to 40 nm.
 10. The device according to claim 7, whereinthe plurality of vias are resized by the formation of the second metallines.
 11. The device according to claim 10, wherein the plurality ofvias are self-aligned in both the first and the second directions. 12.The device according to claim 7, wherein the first and second metallines comprise tungsten (W), cobalt (Co), or copper (Cu).
 13. The deviceaccording to claim 7, wherein the first metal lines have a width of 10nm to 35 nm and a height of 30 nm to 120 nm, inclusive of the nitridecap.
 14. The device according to claim 7, wherein the first SiOC isformed over an oxide layer.
 15. The device according to claim 14,wherein the oxide layer is formed over a silicon substrate.
 16. A devicecomprising: a silicon substrate; an oxide layer formed over thesubstrate; a first silicon oxycarbide (SiOC) layer formed over the oxidelayer; parallel first metal lines recessed in the first SiOC layer andextending in a first direction, the first metal lines comprisingtungsten (W), cobalt (Co), or copper (Cu); an first array of nitridecaps and vias over the first metal lines, formed in the recessed firstSiOC; parallel second metal lines extending in a second directionperpendicular to the first direction, the second metal lines beingformed over the nitride caps, the vias, and the first SiOC layer, andthe second metal lines comprising W, Co or Cu; an second array ofnitride caps formed over the second metal lines; and a second SiOCbetween the second metal lines, down to the first SiOC and the firstmetal lines.
 17. The device according to claim 16, wherein the firstmetal lines have a width of 10 nm to 35 nm and a height of 30 nm to 120nm, inclusive of the nitride cap.
 18. The device according to claim 16,wherein the first and second arrays of nitride caps are formed to athickness of 15 nanometer (nm) to 40 nm.
 19. The device according toclaim 16, wherein the plurality of vias are resized by the formation ofthe second metal lines.
 20. The device according to claim 19, whereinthe plurality of vias are self-aligned in both the first and the seconddirections.